Alpsitec is represented by
Crystec Technology Trading GmbH
Alpsitec France
| CMP, chemical mechanical planarization, polishing equipment | ||
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Alpsitec is represented by
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Chemical mechanical planarization or chemical mechanical
polishing CMP is a process that can remove topography from silicon oxide, poly silicon
and metal surfaces. It is used to planarize oxide, poly silicon or metal layers in order to prepare them for the
following lithographic step, avoiding depth focus problems during illumination of photosensitive layers.
It is the preferred planarization step utilized in deep sub-micron IC manufacturing.u
CMP replaced technologies like boron phosposilicate glass BPSG deposition,
followed by an BPSG anneal step to reflow the low melting doped glass,
or spin-on-glass (SOG) technology. The deposited silica material reflows on the silicon surface
and has to be SOG cured then to remove the remaining solvent and organic components.
The smaller the requested resolution of the structure, the higher is the request for planarity of the surface.
BPSG and SOG do not planarize the layer completely. There is a local height variation between chip
areas of different pattern densities. CMP is the only technique that performs global planarization of the wafer.
Several materials can be planarized by chemical mechanical polishing technologies:
Oxide planarization
Originally CMP was used mainly to planarize silicon dioxide interlevel dielectrics ILDs. Silicon dioxide is deposit thicker than the final thickness requested and the material is then polished back until the step heights are removed. This results in a good flat surface for the next level. The process can be repeated for every level of wiring that is added.
Today another important application is oxide planarization in shallow trench isolation STI technology. The silicon substrate gets a silicon nitride layer on top of it. This stack is patterned and etched. The shallow trenches are then filled with oxide. The CMP step is used to remove all oxide from the top of the silicon nitride layer. After removal of the silicon nitride layer, the transistor can be built by gate oxide and poly-silicon gate formation.
Poly-silicon planarization
Poly-silicon can be polished easily with almost the same types of
polishers, similar pads and slurries as they are used for the
planarization of silicon oxide. Applications are typically the
polishing of poly silicon plugs or vias, removing the poly silicon from
the inter level dielectric ILD and leaving only the plug filled with poly silicon.
Poly silicon planarization can also be used for the end phase of wafer thinning or just for silicon wafer polishing.
Metal planarization
Metals like tungsten, aluminium or copper are used in damascene process technology to fill vias or trenches in order to prepare electrical connections. This technology is named after an ancient technology used for the manufacturing of swords in Damascus.
The tungsten damascene process starts with a fully planarized
dielectric surface that is patterned with vertical contact holes. These holes can be made much smaller and spaced tighter than the
sloped vias of the previous process. Tungsten (W) is then deposited using a chemical vapor
deposition process. The CVD process grows a crystalline tungsten film that fills the holes
from all sides, leaving only a very narrow seam down the middle of the contact
hole. A CMP process is then employed to remove the surface tungsten,
leaving behind the filled contact holes. This polishing process is
designed to be highly selective in removing the tungsten versus the underlying dielectric.
Finally a metal layer is patterned on top of the filled contacts to complete the circuit. This
process is repeated with the oxide planarization step to add each wiring level to an IC.
Beside the usage to prepare vias for connecting two wiring levels,
the damascene process can also be used with trenches patterned in the
dielectric to form the wiring themselves. Copper is often used for this process. A shallow
trench is etched in the dielectric in the shape of the desired wire,
the copper is deposited on the wafer by electrochemical deposition ECD, and the CMP
process selectively removes the material to leave the trench filled.
In the dual damascene process, both the wiring level and the interlevel
connections are created with a single CVD or ECD step and a single polishing step.
All metal layers have to be annealed after deposition or planarization.
The copper anneal process is described on a separate page.
Chemical mechanical planarization is a process of smoothing and planing surfaces with the combination of chemical and mechanical forces, a hybrid of chemical etching and free abrasive polishing. Mechanical grinding alone causes too much surface damage, while wet etching alone cannot attain good planarization. Most chemical reactions are isotropic and etch different crystal planes with different speed. CMP involves both effects at the same time.
A typical CMP tool consists of a rotating platen, that is covered
by a pad. The wafer is mounted upside down in a carrier on a backing
film. The retaining ring keeps the wafer in the correct horizontal
position. Both, the platen and the carrier are rotating. Good speed
control is important. The carrier is also oscillating. For
loading and unloading a robot system is installed. During loading
and unloading the wafer is kept in the carrier by vacuum.
During chemical mechanical polishing, pressure is applied by down force
on the carrier, transferred to the the carrier through the carrier axis
and a gimbal mechanism. Beside that also gas pressure or back pressure
is loaded on the wafer. The fact that high points on the wafer are
subjected to higher pressures compared to lower points, hence, the removal rates there
are enhanced and planarization is achieved.
The slurry is supplied from above on the platen. Process
relevant are the grain size and material of the abrasive component and
the pH control of the slurry. Normally alkalic conditions are used.
Thermal management is very important for CMP. The polishing speed
depends much on the temperature and during CMP heat is generated by
reaction heat and abrasive friction. Therefore the platen has a
temperature control system, than can adjust the temperature between
10°C and 70°C. This is done either by back spray technology as
shown in the graphic or by contact with a water cooled support and
transmission ring, vacuum locked to the platen.
A typical CMP system also involves a pad conditioning tool as well as a tool for the wafer cleaning after CMP. Also various end point detection systems can be integrated in the CMP tool. This can be done by measuring platen and carrier motor current and platen temperature by IR sensor. As an option the Nova oxide measurement system can be integrated.
Crystec Technology Trading GmbH, Germany, www.crystec.com, +49 8671 882173, FAX 882177
Alpsitec is semiconductor equipment and technology company. It has
been founded in 2001 as a spin-off company of Steag, and is located in Grenoble, France. The main
activities are the design, production and installation of machines for chemical
mechanical planarization of silicon wafers and, as a partner of Cognex, the
integration of pattern recognition systems in production lines.
Crystec represents Alpsitec for its CMP equipment. These machines, installed by Alpsitec and its predecessor at
universities, research institutes and industrial customers, are well known and enjoy an excellent reputation.
Alpsitec CMP equipment is designed for research and development R&D and pilot line production. Therefore it has been designed for high performance, high flexibility, small footprint, ease of operation and low costs. Stand alone machines and modular designs are available. Changing silicon wafer sizes is easy; also special shapes of samples, e.g. rectangular wafers can be handled, using special carriers. Here follows an overview, description and comparison of the available models:
The Pcox 200 S has a unique position on the R&D planarization market. Indeed the machine is identical to its production oriented parents from the Pcox20X family. The Pcox20X range presents a series of modular machines which offers configurations including 2, 3 or 4 polishing modules. The Pcox 200 S is one of these modules used in stand-alone form for process development It offers all the specifications of the production machine:
• Complete control by computer and PLC
• Automatic loading and unloading of the polishing head
• Multi polishing steps
• Compatibility 4" to 8"
• Ex-situ and in-situ conditioning
• Integrated slurry pumps
• Unique quick exchange of platen, polishing carriers and conditioning tools.
Its structure offers the same productivity specifications as a module included in a Pcox20X machine
although with manual loading of the wafer to save space and cost.
Other assets :
• Direct transfer of processes developed on the Pcox200 S to a Pcox20X production machines.
• Possible and easy evolution of a Pcox200 S module into a Pcox20X machine ensuring long tool life without obsolescence.
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| Handling station including 3 cassettes, wafer handling robot and additional linear transfer robot | Original PCox 200S |
Additional polish module in the PCox202S |
Additional polish module in the PCox203S |
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The E550 is a stand alone planarization tool for the semiconductor
industry. Its two-Plate design and the cassette to cassette handling
makes it a perfect tool for a semiconductor production line. The
modular design also allows it to be easily applied to research and
development. The tool is capable of polishing and planarization of
single wafers up to 200 mm. Easy and quick handling is one of the most
advanced features of this planarization-tool:
Software is transparent and flexible, cleaning is easy due to the removable splash-guard, DI-nozzles and a DI-pistol, access from three sides to the polishing area completes the easy maintenance and enables a convenient pad and carrier exchange.
POLISHING STATION
The wafer is loaded and unloaded from the carrier via the
dual transfer palette. First the wafer is polished on the primary plate
with a diameter of 550 mm. Next the wafer can be polished on the final
plate with a diameter of 350 mm. The primary plate is held by vacuum
for fast and easy assembly. The cleaning area is located above the
final plate, for rinsing the wafer and the carrier. This is also the
load position for the carrier. The conditioning tool of the primary
plate can be configured with a diameter of up to 238 mm, which is
immerged in DI water during the polishing cycle. This conditioner can
be equipped either with a brush or a diamond disc. The conditioner for
the final plate consists out of a linear brush.
The E460 is designed for polishing and planarization of single wafers with diameters
between 2" and 8". The optimal use of E460 is in the field of research and development application,
as well as small scale production requirements due to the machine's flexibility.
The E460 offers 5 process steps. Each step offers a specific set of parameters.
The tool allows manual loading with automatic polishing control.
Our standard wafer mounting uses vacuum and back pressure but any kind of mounting is possible:
wax, templates. Special carrier arrangement can be realized to fit to customers requirements.
The tool is equipped with an automatic conditioning device. Connectors for an easy and fast
end point detection are placed on the machine back side.
Since 2009 this reliable machine is now available bis a PC control (right picture)
Special advantages:
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