Analyse de défaillance des ICs circuits intégrés par elèvement, elimination (delayering) des couches et dépassivation par gravure de plasma (RIE gravure des ions réactifs).

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Analyse de défaillance des circuits intégrés

Failure analysis of integrated circuits

Failure analysis of intergrated circuits (ICs) is used in order to find hidden defects like open circuits or short cuts in integrated circuits. In order to find them, a chip needs to be opened. Layer by layer has to be removed, so that the metal lines can be exposed and investigated by raster electron microskopy. Usually small and flexible plasma etchers are used for this job, same models that are used also for research and development. Using an ICP plamsa source can speed up this process. Also ICP systems are more selective and create lower damage compared to a standard RIE system. Delayering of the integrated circuit IC is usually performed either by skeleton etching or by sequential removal of all layers.

Skeleton Etch: Anisotropic removal of dielectric layers

When all dielectric layers are removed anisotropically down to the silicon surface, then metal conductor lines remain on top of pedestals of dielectric material. Anisotropic etch avoids undercut of the metal lines, and therefore delamination. Defects in the metal lines can be examined then by raster electron microscopy.

IC failure analysis skeleton etch

Sequential removal of layers

In many cases skeleton etching is successful. However sometimes defects are underneath metallic layers and in this case skeleton etching fails and sequential removal of metallic and dielectric layers is necessary. Careful selection of process recipes is necessary. Sometimes time etching is necessary if a precise etch stop cannot be achieved by selection of etching gas.

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